Successive approximation is one of the basic principles for analog-to-digital conversion. The general functionality and operation of SAR analog-to-digital converters (ADCs) is well known in the art. Generally, SAR ADCs compare the analog input voltage to reference voltage levels, which can be generated by a digital-to-analog converter (DAC). During a first clock cycle, the sampled input voltage is compared to half the reference voltage output by the DAC. If the input voltage is greater than half the reference voltage, then a respective bit decision relating to the most significant bit (MSB) is made. During the next clock cycle, the input voltage is compared to three quarters or one quarter of the reference voltage in accordance with the preceding MSB decision, and a further bit decision is made relating to the next less significant bit (MSB-1). The conversion procedure carries on accordingly, and the DAC output voltage converges successively to the analog input voltage, while evaluating one bit during each clock cycle. A corresponding block diagram is shown in FIG. 1. The SAR ADC is arranged such that, when the conversion is completed, the digital number input to the DAC represents the digitized input voltage.
Since precise DAC voltages are needed, capacitive DACs (CDACs) are often used, which include a plurality of capacitors. The analog input voltage can be sampled directly on the capacitors of the CDAC, such that a charge corresponding to the size of the capacitors and proportional to the amplitude of the input voltage is present on the sampling capacitors. The sampled charge is redistributed stepwise among the capacitors of the CDAC. The capacitors are connected together on one side to a common node. The magnitude of the input voltage is basically determined by selectively and consecutively switching the other sides of the capacitors between different reference voltage levels and comparing the established voltage level on the common node to a mid voltage level. The capacitor having the largest capacitance will be the first to be connected to a specific reference voltage level, while the remaining capacitors are connected to another reference voltage level. Then the voltage on the common node, which is connected to a comparator input is compared with the mid voltage level, such that the output of the comparator represents the bit values of the digital output word bit by bit, starting with the most significant bit (MSB). In accordance with the comparator output (i.e., the comparison result), the capacitors are consecutively connected one-by-one to either the first or the second reference voltage level and remain in this position during the next conversion steps. The intermediate results are stored in a register.
Up-to-date electronic devices, and corresponding semiconductor manufacturing processes, typically use supply voltages of 5 V or less in order to save power and to gain speed. The supply voltage limits the input signal range of the ADCs. In order to convert a +/−10 V input signal, which is a typical industrial standard, the signal is divided either with a resistive divider or with a capacitive divider, so as to fit the input signal voltage range into the comparator's input voltage range, which is basically between ground and the supply voltage level. However, the division of the input signal decreases the signal-to-noise ratio (SNR). The least significant bit (LSB) for a 5 V supply voltage range and an input range of +/−10 V (i.e., a division by 4 is required) on a 16-bit converter corresponds to 76 PV, although it could amount to 305 μV if the signal was not divided. A typical up-to-date 16-bit SAR converter has a noise level that corresponds to 2 to 6 LSB at the output for any DC input voltage. In order to handle the relatively large input voltage range, high-voltage transistors are required. Typical 5 V semiconductor manufacturing processes provide high-voltage transistors so that ADCs are available that have a high input voltage range even on a low voltage core that runs, for example, with the 5 V supply voltage. However, dividing the input signal is always necessary, thereby decreasing the achievable SNR.